Kernel driver `fscscy.o'
======================

Status: Beta
   Tested with motherboard D1230
   Should also work with D1204, D1306 and D1307
   
   Think twice before you're using the write mode of some
   variables, especially the watchdog (Not my comment, but it makes
   good sense to observe :-)
	

Supported chips:
  * Fujitsu Siemens Scylla chip
    Prefix `fscscy'
    Addresses scanned: I2C 0x73 

Author: Martin Knoblauch <mkn@teraport.de>

Acknowledgement:
     This code has been greatly inspired by Hermann Jung <hej@odn.de>
     and his work on the Poseidon driver (fscpos)


Module Parameters
-----------------

* force: short array (min = 1, max = 48)
  List of adapter,address pairs to boldly assume to be present
* ignore: short array (min = 1, max = 48)
  List of adapter,address pairs not to scan
* ignore_range: short array (min = 1, max = 48)
  List of adapter,start-addr,end-addr triples not to scan
* probe: short array (min = 1, max = 48)
  List of adapter,address pairs to scan additionally
* probe_range: short array (min = 1, max = 48)
  List of adapter,start-addr,end-addr triples to scan additionally


Description
-----------

This driver implements support for the Fujitsu Siemens Scylla chip.
The code is based on the "fscpos" driver for the FSC Poseidon chip.
In fact, it seems the Scylla is a superset of the "Poseidon", "Poseidon II"
and "Hydra" chips.

The register readings/setting have been deduced from the 'Register Set
Specification BMC Poseidon based Systemboard' by Fujitsu Siemens and the
"sbbmon.ini" file from the Fujitsu-Siemens ServerView software.

The scylla chip implements a hardware based system management,
e.g. for controlling fan speed and core voltage.
There is also a watchdog counter on the chip which can trigger
an alarm and even shutdown the system. See above for more details about using
the watchdog feature.

The chip provides four temperature values (cpu0/1, motherboard and auxiliary),
three current values (12 volt, 5 volt and battery) and up to
six fans (power supply, cpu and auxiliary). 

Temperatures are measured in degrees Celcius. The resolution is 1 degree.
In addition to state and actual temperature, the temperature sensors also export
a LIMIT temperature for each sensor. The meaning of the information itself is
obvious. The rest is guesswork. It likely triggers an alarm/event as soon as it is
reached. The authors feeling is that it is even a writeable register. But beeing of
the cautios kind he did not implement writing the LIMIT resister. The driver itself
keeps track of the minimum and maximum temperatures since module load. The more often
the module is accessed, the more meaningful these values are. 

FAN rotation speeds are reported in RPM (rotations per minute). 
The value can be divided by a programmable divider (1, 2, 4 or 8) which 
is stored on the chip.

Voltage sensors (also known as IN sensors) report their values in volts.

All values are reported as final values from the driver. 
There is no need for further calculations.


Using The Watchdog
------------------

This part was mostly contributed by A'rpi <arpi@thot.banki.hu>. Thanks!
I (Jean Delvare) edited the text for greater clarity, mainly to integrate
the e-mail exchange I and A'rpi had as a sequel of the original report.
Here it goes.

I've spent few hours experiencing with the watchdog feature of the Fujitsu
Siemens server board (don't ask the model name, what I know is that it uses
Serverworks CSB5 chipset) using lm_sensors' fscscy driver.

OK, so there is /proc/sys/dev/sensors/fscscy-i2c-0-73/wdog, containing 3
8-bit values for the 3 watchdog registers.

The first one is the time counter, it counts backwards. It's in 2 seconds
base, so writting 30 there means 60 seconds delay. It seems the whole range
(0 to 255) is supported, so up to 510 seconds (8.5 minutes). Writting 0 means
immediate hardware reset. The value you can read back is the same as you wrote
there, not the current value of the counter (as I expected).

The second number is supposed to be a state register. It doesn't matter what
value I put there. It's always 0. Even if I write a non-zero value there, i got
0 back. Maybe it's non-zero at the moment of reset :)

The third is the control register, with 5th (value 16), 6th (value 32) and 8th
(value 128) bits used only. If I write 16 or 144 (128+16), it means system
reset when the counter reaches 0. If I add 32 (for a value of 48 or 176), no
reset will occure.

So, the world's simplest watchdog using this mainboard:

while true ; do
  echo 30 0 16 > /proc/sys/dev/sensors/fscscy-i2c-0-73/wdog
  sleep 10
done

It does hardware reset after 1 minute, if this script is killed or system
hang-up occurs. Adjust the 30 and 10 values according to you needs, but
remember you must sleep less than the reset countdown time (here, 30*2-10
gives us a 50 seconds margin, which is more than enough).

Also note that BIOS has a strange setting, named 'OS Boot Retry Count', set
to 0 by default, it changes watchdog behaviour to power off instead of reset.
(0=poweroff 1..7=reset). It took me a while to find this. This behavior is
probably related to the "Reset Limit" parameter defined by the ACPI
specification (3.3.24 System Reset (Type 23)). It sets how many unintentional
resets can be performed in a row before giving up (and shut down).

Please add the above to the documentation (doc/chips/fscscy), so i can save
a few hours of resetting for other people :)


Chip Features
-------------

Chip `fscscy'
          LABEL     LABEL CLASS   COMPUTE CLASS ACCESS MAGNITUDE
            rev	           NONE	           NONE      R     0
          event            NONE            NONE      R     0
        control            NONE            NONE     RW     0
         volt12            NONE	           NONE      R     2
          volt5            NONE	           NONE      R     2
       voltbatt            NONE	           NONE      R     2
          temp1            NONE	           NONE      R     0
          temp2            NONE	           NONE      R     0
          temp3            NONE	           NONE      R     0
          temp4            NONE	           NONE      R     0
    temp1_state           temp1	          temp1     RW     0
    temp2_state           temp2	          temp2     RW     0
    temp3_state           temp3	          temp3     RW     0
    temp4_state           temp4	          temp4     RW     0
    temp1_lim             temp1	          temp1     R*     0
    temp2_lim             temp2	          temp2     R*     0
    temp3_lim             temp3	          temp3     R*     0
    temp4_lim             temp4	          temp4     R*     0
    temp1_min             temp1	          temp1      R     0
    temp2_min             temp2	          temp2      R     0
    temp3_min             temp3	          temp3      R     0
    temp4_min             temp4	          temp4      R     0
    temp1_max             temp1	          temp1      R     0
    temp2_max             temp2	          temp2      R     0
    temp3_max             temp3	          temp3      R     0
    temp4_max             temp4	          temp4      R     0
           fan1            NONE	           NONE      R     0
           fan2            NONE	           NONE      R     0
           fan3            NONE	           NONE      R     0
           fan4            NONE	           NONE      R     0
           fan5            NONE	           NONE      R     0
           fan6            NONE	           NONE      R     0
       fan1_min            fan1	           fan1     RW     0
       fan2_min            fan2	           fan2     RW     0
       fan3_min            fan3	           fan3     RW     0
       fan4_min            fan4	           fan4     RW     0
       fan5_min            fan5	           fan5     RW     0
       fan6_min            fan6	           fan6     RW     0
     fan1_state            fan1	           fan1     RW     0
     fan2_state            fan2	           fan2     RW     0
     fan3_state            fan3	           fan3     RW     0
     fan4_state            fan4	           fan4     RW     0
     fan5_state            fan5	           fan5     RW     0
     fan6_state            fan6	           fan6     RW     0
    fan1_ripple            fan1	           fan1     RW     0
    fan2_ripple            fan2	           fan2     RW     0
    fan3_ripple            fan3	           fan3     RW     0
    fan4_ripple            fan4	           fan4     RW     0
    fan5_ripple            fan5	           fan5     RW     0
    fan6_ripple            fan6	           fan6     RW     0
    wdog_preset            NONE	           NONE     RW     0
     wdog_state     wdog_preset	    wdog_preset     RW     0
   wdog_control     wdog_preset	    wdog_preset     RW     0
	
  R*: Maybe writable, but due to lack of documentation the author did not dare
      to implement it :-)


          LABEL                           FEATURE SYMBOL     SYSCTL FILE:OFFSET
            rev	                      FSCSCY_SYSCTL_REV              rev:1
          event                     FSCSCY_SYSCTL_EVENT            event:1
        control                   FSCSCY_SYSCTL_CONTROL          control:1
         volt12                  FSCSCY_SYSCTL_VOLTAGE1            volt0:1
          volt5                  FSCSCY_SYSCTL_VOLTAGE2            volt1:1
       voltbatt                  FSCSCY_SYSCTL_VOLTAGE3            volt2:1
          temp1                     FSCSCY_SYSCTL_TEMP1            temp0:2
          temp2                     FSCSCY_SYSCTL_TEMP2            temp1:2
          temp3                     FSCSCY_SYSCTL_TEMP3            temp2:2
          temp4                     FSCSCY_SYSCTL_TEMP4            temp3:2
    temp1_state               FSCSCY_SYSCTL_TEMP1_STATE            temp0:1
    temp2_state               FSCSCY_SYSCTL_TEMP2_STATE            temp1:1
    temp3_state               FSCSCY_SYSCTL_TEMP3_STATE            temp2:1
    temp4_state               FSCSCY_SYSCTL_TEMP4_STATE            temp3:1
    temp1_lim                 FSCSCY_SYSCTL_TEMP1_LIM              temp0:3
    temp2_lim                 FSCSCY_SYSCTL_TEMP2_LIM              temp1:3
    temp3_lim                 FSCSCY_SYSCTL_TEMP3_LIM              temp2:3
    temp4_lim                 FSCSCY_SYSCTL_TEMP4_LIM              temp3:3
    temp1_min                 FSCSCY_SYSCTL_TEMP1_MIN              temp0:4
    temp2_min                 FSCSCY_SYSCTL_TEMP2_MIN              temp1:4
    temp3_min                 FSCSCY_SYSCTL_TEMP3_MIN              temp2:4
    temp4_min                 FSCSCY_SYSCTL_TEMP4_MIN              temp3:4
    temp1_max                 FSCSCY_SYSCTL_TEMP1_MIN              temp0:5
    temp2_max                 FSCSCY_SYSCTL_TEMP2_MIN              temp1:5
    temp3_max                 FSCSCY_SYSCTL_TEMP3_MIN              temp2:5
    temp4_max                 FSCSCY_SYSCTL_TEMP4_MIN              temp3:5
           fan1                      FSCSCY_SYSCTL_FAN1             fan0:4
           fan2                      FSCSCY_SYSCTL_FAN2             fan1:4
           fan3                      FSCSCY_SYSCTL_FAN3             fan2:4
           fan4                      FSCSCY_SYSCTL_FAN4             fan3:4
           fan5                      FSCSCY_SYSCTL_FAN5             fan4:4
           fan6                      FSCSCY_SYSCTL_FAN6             fan5:4
       fan1_min                  FSCSCY_SYSCTL_FAN1_MIN             fan0:2
       fan2_min                  FSCSCY_SYSCTL_FAN2_MIN             fan1:2
       fan3_min                  FSCSCY_SYSCTL_FAN3_MIN             fan2:2
       fan4_min                  FSCSCY_SYSCTL_FAN4_MIN             fan3:2
       fan5_min                  FSCSCY_SYSCTL_FAN5_MIN             fan4:2
       fan6_min                  FSCSCY_SYSCTL_FAN6_MIN             fan5:2
     fan1_state                FSCSCY_SYSCTL_FAN1_STATE             fan0:1
     fan2_state                FSCSCY_SYSCTL_FAN2_STATE             fan1:1
     fan3_state                FSCSCY_SYSCTL_FAN3_STATE             fan2:1
     fan4_state                FSCSCY_SYSCTL_FAN4_STATE             fan3:1
     fan5_state                FSCSCY_SYSCTL_FAN5_STATE             fan4:1
     fan6_state                FSCSCY_SYSCTL_FAN6_STATE             fan5:1
    fan1_ripple               FSCSCY_SYSCTL_FAN1_RIPPLE             fan0:3
    fan2_ripple               FSCSCY_SYSCTL_FAN2_RIPPLE             fan1:3
    fan3_ripple               FSCSCY_SYSCTL_FAN3_RIPPLE             fan2:3
    fan4_ripple               FSCSCY_SYSCTL_FAN3_RIPPLE             fan3:3
    fan5_ripple               FSCSCY_SYSCTL_FAN3_RIPPLE             fan4:3
    fan6_ripple               FSCSCY_SYSCTL_FAN3_RIPPLE             fan5:3
    wdog_preset               FSCSCY_SYSCTL_WDOG_PRESET             wdog:1
     wdog_state                FSCSCY_SYSCTL_WDOG_STATE             wdog:2
   wdog_control              FSCSCY_SYSCTL_WDOG_CONTROL             wdog:3

