{% extends "base.html" %} {% from 'components.html' import icon %} {% block title %}Library guide{% endblock %} {% block content %}
The benchmark library
Understand the abstraction levels, gate libraries, clocking schemes, and file formats behind MNT Bench.
Explore benchmarksFrom logic to layout
Open an illustration to see the full-size reference.
Two technologies
Benchmarks are provided for two different gate libraries.
Controlling the flow
Up to five different clocking schemes are available.
Working with your download
Downloads are ZIP archives containing network-level Verilog
.v files and gate-level fiction .fgl files.
The filenames describe the configuration of each layout.
Not every benchmark is necessarily available for every possible configuration of the available options. For example, for large circuits, layouts using the USE clocking scheme have not been found yet.
| Level | Filename | Example |
|---|---|---|
| Gate-level | <benchmark_identifier>_<library>_<clocking_scheme>_<algorithm>_<optimized>_<input-ordered>_<cost_objective>.fgl |
|
| Best gate-level layout | <benchmark_identifier>_<library>_BEST.fgl |
mux21_ONE_BEST.fgl |
| Network level | <benchmark_identifier>.v |
mux21.v |
The work behind the library
Explore the original benchmark collections, design methods, and optimizations.
Additional FCN design methods. Inclusion here does not imply that layouts generated with these methods are available in MNT Bench.