Metadata-Version: 2.4
Name: uvm-testbench-generator
Version: 0.1.2
Summary: Tkinter-based UVM testbench generator that scaffolds SystemVerilog testbenches from a DUT.
Author: atifafzal786
License: MIT License
        
        Copyright (c) 2026 Atif Afzal
        
        Permission is hereby granted, free of charge, to any person obtaining a copy
        of this software and associated documentation files (the "Software"), to deal
        in the Software without restriction, including without limitation the rights
        to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
        copies of the Software, and to permit persons to whom the Software is
        furnished to do so, subject to the following conditions:
        
        The above copyright notice and this permission notice shall be included in all
        copies or substantial portions of the Software.
        
        THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
        IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
        FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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        LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
        OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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Project-URL: Repository, https://github.com/atifafzal786/UVM-Testbench-Generator
Project-URL: Documentation, https://github.com/atifafzal786/UVM-Testbench-Generator/tree/main
Keywords: uvm,systemverilog,testbench,generator,tkinter
Classifier: Programming Language :: Python :: 3
Classifier: License :: OSI Approved :: MIT License
Classifier: Operating System :: OS Independent
Requires-Python: >=3.9
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: pillow>=10
Dynamic: license-file

# Testbench Ecosystem

Tkinter-based UVM testbench generator that guides you from DUT import to a complete SystemVerilog scaffold. Configure interface, transaction, agent, scoreboard, environment, sequences, tests, and top; track workflow status, preview every generated file, and export a structured project folder (src/, tb_pkg.sv, top.sv, filelist.f, manifest.json). SV!

## What this is

This project is a desktop GUI that helps you build a multi-file UVM-style testbench starting from a DUT (`*.sv`) file. The app walks you through the typical UVM building blocks (interface → transaction → agent → environment → test → top), then generates a structured output folder ready to compile/simulate.

## Quick start

1) Install Python (3.9+) with Tkinter available.
2) Install dependencies:

```bash
pip install -r requirements.txt
```

3) Run the app:

```bash
python testbench_generator.py
```

Badges

- Build: [![CI](https://github.com/atifafzal786/UVM-Testbench-Generator/actions/workflows/python-ci.yml/badge.svg)](https://github.com/atifafzal786/UVM-Testbench-Generator/actions)

Docs & support

See `USAGE.md` and `USER_GUIDE.md` for full documentation and walkthroughs.

## Output structure (generated)

When you click **Generate Testbench**, the app writes into:

`<Output Directory>/<Project Name>/`

Common files:

- `manifest.json` (what was generated)
- `filelist.f` (minimal compile list)
- `README.md` (generated project README)
- `src/interface.sv`
- `src/transaction.sv`
- `src/sequence.sv`
- `src/agent.sv` (plus optional `driver.sv`, `monitor.sv`, `sequencer.sv`)
- `src/scoreboard.sv`
- `src/environment.sv`
- `src/test.sv`
- `src/tb_pkg.sv`
- `src/top.sv`

## Docs

- `USAGE.md` — fast workflow steps
- `USER_GUIDE.md` — detailed user manual
- `GITHUB_DESCRIPTION.txt` — 350-character repo description

## Notes

- The runnable app entrypoint is `testbench_generator.py`.
- This repo may contain older/alternate UI modules (extra splash screens, footers, dashboards). They are not used by the current entrypoint unless you wire them in.

